1. Field of the Invention
The present invention relates to an apparatus employing a plurality of graphic processors for simultaneously processing graphic data and displaying a graphic image.
The fields of computer graphics, CAD and CAM, employ a graphic display apparatus that displays a large quantity of graphic data on a screen and changes the graphic data in real time. There is a technique of distributing graphic data from a main memory to the individual memories of graphic processors that simultaneously process the graphic data. The processing speed of each of the graphic processors depends on the type and size of the graphic data to process. Accordingly, since some of the graphic processors may have no data to process while the others still have data, it is required to efficiently drive the graphic processors to simultaneously process graphic data.
2. Description of the Related Art
FIGS. 4(A) and 4(B) show a graphic data parallel processing and displaying apparatus according to the prior art, and FIG. 5 is a flowchart showing the operations of the apparatus.
The apparatus of FIG. 4(A) is employed in the fields of computer graphics, CAD and CAM. This apparatus changes, corrects, and displays a large quantity of graphic data in real time. The apparatus also carries out shading on the graphic data, to provide a graphic image having reality with light and shade. This apparatus involves a great number of calculations.
The apparatus of FIG. 4(A) employs a plurality of graphic processors and distributes graphic data to them, which then simultaneously process the data.
In FIG. 4(A), the apparatus includes a graphic data controller 100, a main memory 101 for storing graphic data, a bus 102, half-full flags 103, FIFO (first-in first-out) memories 104a to 104d having the same structure, graphic processors 105a to 105d for simultaneously processing distributed graphic data, and a display 106 for receiving processed data from the processing units 105a to 105d and displaying a graphic image.
The half-full flags 103 correspond to the FIFO memories 104a to 104d, respectively. If any of the FIFO memories 104a to 104d is holding an amount of data larger than a predetermined quantity, for example, half of the full capacity, the corresponding flag is set to 1 (one), and if not, the flag is reset to 0 (zero).
To control the flags 103, each of the FIFO memories 104a to 104d has an arrangement as shown in FIG. 4(B) that sets or resets the corresponding flag depending on whether or not the quantity of data remaining in the FIFO memory is at a half-full point.
The operations of the prior art of FIGS. 4(A) and 4(B) will be explained with reference to the flowchart of FIG. 5.
Step S1 sets a half-full point in each of the FIFO memories. Step S2 reads graphic data from the main memory 101. Step S3 determines the type of the graphic data. The graphic data are coordinate data or attribute data. The coordinate data indicate the shape of a figure and are independently processed by the graphic processor 105a to 105d. The attribute data indicate, for example, the color of the figure and must be simultaneously processed by the graphic processors 105a to 105d.
If the step S3 determines that the graphic data are the coordinate data, step S4 selects each of the FIFO memories 104a to 104d having the zero half-full flags. If there are no FIFO memories having the zero half-full flag, the step S4 waits until any one of the half-full flags becomes 0. During this waiting period, the graphic processors 105a to 105d process coordinate data stored in the respective FIFO memories 104a to 104d. The quantities of the data in the FIFO memories decrease accordingly. If any one of the half-full flags becomes 0, step S5 transfers the coordinate data from the main memory 101 to the FIFO memory corresponding to the zero flag. The quantity of the transferred data is equal to the capacity of the FIFO memory minus a capacity corresponding to the half-full point. Step S6 determines if there are still coordinate data to be transferred to the FIFO memories. If there are, the flow returns to the step S4, and if not, the flow returns to the step S2 to read the next graphic data from the main memory 101.
If the data read in the step S2 are the attribute data, step S7 refers to the half-full flags and waits until every flag becomes 0. Since it usually takes a long time to process the attribute data, it is preferable to process them collectively. This is the reason for waiting until every half-full flag becomes 0.
After all of the half-full flags become 0, step S8 writes the attribute data into all FIFO memories. At this time, the quantity of the attribute data to be written is set so as not to exceed the amount of free space in each FIFO memory. Step S9 determines if there are still attribute data to be written into the FIFO memories. If there are, the flow returns to the step S7, and if not, the flow returns to the step S2 to read the next graphic data from the main memory 101.
The reason why the prior art employs the half-full flags will be explained with reference to FIG. 4(B).
If a point A, close to a full point, in the FIFO memory is employed to set and reset the corresponding flag, the quantity of data to be written into the FIFO memory is always small when the flag indicates that there are no data at the point A. Namely, the amount of free space corresponding to the point A is small. On the other hand, if a point B, close to an empty point, in the FIFO memory is employed to set and reset the flag, it takes a long time until the flag becomes 0. Accordingly, the half-full point, i.e., an average point, is more efficient than the point A or B in setting and resetting the flag.
In this way, the graphic processors 105a to 105d independently process graphic data if they are coordinate data. It is possible to transfer the coordinate data to any of the FIFO memories if the corresponding half-full flag is 0. If the graphic data are attribute data, however, they are transferrable to the FIFO memories only when all of the half-full flags are 0. Namely, the attribute data involve a long waiting time and cause efficiency to deteriorate.
The prior art causes fluctuations in the processing speed of the graphic processors depending on the type and size of graphic data. This may cause no problem when the graphic data are coordinate data that are separately transferable to the graphic processors through the FIFO memories. If the data are attribute data that must be simultaneously transferred to the graphic processors through the FIFO memories, it is necessary to wait until the half-full flags of all of the FIFO memories are reset to 0. Namely, it must wait until the slowest graphic processor is released from a half-full state. Until this occasion, the other graphic processors will have no data to process, causing a waste of time. This will deteriorate the performance of the apparatus.